1. Field of the Invention
The present invention relates to a method for making buried bottom electrodes, and particularly relates to a method for making the bottom electrode of a buried capacitor, which can improve the vertical leakage current.
2. Description of the Prior Art
Deep trench has been widely used in advanced DRAM technology, wherein the capacitors are buried in the trench. The electronic property of the DRAM is based on the charge-storing capacity, which is determined by the area of the electrodes of the capacitor. Recently, the effective region for bottom electrodes of the buried capacitors can be defined by photolithography and etching processes. The processes for fabricating the traditional buried capacitor are illustrated in FIG. 1A to FIG. 1E.
Referring to FIG. 1A, a P-type Si substrate is provided. A pad oxide layer 110 with a thickness of about 45 .ANG. is formed on the substrate 100 by way of thermal oxidation. A silicon nitride layer 120 and a TEOS layer 130 are deposited on the pad oxide layer 110 in series. Then, a photoresist pattern 140 with an opening for etching is formed on the TEOS layer 130 by photolithography and etching processes.
Referring to FIG. 1B, by using the photoresist pattern 140 as an etching mask, the exposed TEOS layer 130 within the opening, and the silicon nitride layer 120, the pad oxide layer 110 underlying the exposed TEOS layer 130 are removed by dry-etching to pattern a hard mask 150. Then, the photoresist pattern 140 is removed. The substrate 100 unshielded by the hard mask 150 is etched to form a trench 160 with a depth ranging from 7 .mu.pm to 8 .mu.m.
Referring to FIG. 1C, a N-type Si-glass, such as AsSG, is deposited to comfortably cover the TEOS layer 130 and the side wall of the trench 160. Then, a photoresist layer 180 is formed on the Si substrate 170, and filled the trench 160.
Referring to FIG. 1D, a photoresist 180 with a thickness of about 4.about.6 .mu.m and the remained N-type Si glass 170 are left on the bottom of the trench 160 to define the predetermined region 185 for the bottom electrode by etching back the photoresist 180 and the N-type Si glass 170.
Referring to FIG. 1E, a TEOS layer with a thickness ranging from 100 .ANG..about.300 .ANG. (unshown) is deposited after removing the photoresist layer 180. Then, an annealing treatment is applied to drive the N-type impurities within the Si-glass 170 to diffuse into the bottom electrode region 185 through the side wall of the trench 160, thus a bottom electrode 190 consisting of N-type diffusion region is generated.
However, when wet etching is used to define the predetermined region 185 for the bottom electrode 190, some remains of the N-type Si-glass 170 will be left beside the predetermined region 185 for the bottom electrode, and particularly the side wall of the trench upside the predetermined region 185 for the bottom electrode 190. The N-type impurities within the remains left beside the predetermined region 185 for the bottom electrode 190 will be driven to diffuse into the P-type substrate 100 during annealing, thus a non-desired N-type diffusion region connecting to the bottom electrode 190 is generated. Accordingly, a serious leakage current will appear in the buried capacitor comprising the bottom electrode made according to the above-mentioned method.